System for optimizing anti-fuse repair time using fuse ID

ABSTRACT

A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to the field of testing asemiconductor memory chip and more specifically to optimizing repairtime using a fuse identifier associated with the semiconductor memorychip.

[0003] 2. Discussion of the Related Art

[0004] In order to ensure that a semiconductor device, such as a DRAM,is reliable, multiple tests are performed on the device before and afterpackaging.

[0005] A DRAM includes an array of memory cells or bits in rows andcolumns. After packaging, a plurality of tests are performed on thedevice in order to determine whether there is a defect in the array ofbits that will fail over time. For example, burn-in testing is performedto accelerate failure using voltage and temperature stress. When afailed memory cell is detected, the row or column in which the failedmemory cell is located is substituted by a redundant row or column,respectively. After packaging, this substitution is performed usingantifuses in the memory chip.

[0006] Antifuses are capacitors including two conductive layers spacedby a thin insulative material, such as silicon nitride. Under normalbiasing conditions, no DC current flows through the antifuse. Uponapplication of an excessive bias across the two conductive layers,however, the thin insulative material breaks down, thereby shorting thetwo conductive layers. Thus, redundant memory elements coupled to theantifuses can be selectively connected to circuiting external to thememory array by applying the excessive bias to desired antifuses.

[0007] If a memory chip fails any one of the tests, it is placed in afailure bin and becomes a candidate for antifuse repair. During therepair step, redundancy analysis is performed on each of the failedmemory chips which involves repeating tests in order to identifyspecific bits that have failed. Once a failed bit is located, either theentire row or column in which it is located is replaced with acorresponding redundant row or column. Redundancy analysis has half thethroughput of the initial testing analysis because the initial analysistypically tests 64 sites wide on a chip such as 16M DRAM whileredundancy analysis only tests 32 sites wide on the memory chip.

[0008] Due to the relatively large amount of time required to performredundancy analysis, only a subset of tests are run, such as the tenmost commonly failed tests. However, faulty memory cells in chipsfailing tests not among these top ten failing tests will not be detectedand repaired during redundancy analysis.

SUMMARY OF THE INVENTION

[0009] In accordance with the purpose of the invention, as embodied andbroadly described herein, a method is provided for testing integratedcircuits or semiconductor memory chips, such as DRAMs, having aplurality of bits or memory cells. Each memory chip has a uniqueidentifier, preferably a fuse identifier having a series of selectivelyblown fuses corresponding to a unique binary number, located on thememory chip. The information contained in the fuse identifier is alsostored in a database. Tests are performed on the memory chips and when amemory chip fails a test, the memory chip is placed in a repair bin andthe failed test identifier is stored in the database with the associatedmemory chip identifier. In order to repair the memory chip, failed testdata are read out of the database and only selected tests which thechips failed are again performed on the failed memory chip in order todetermine which bit in the memory chip is faulty. The failed bits arethen repaired preferably by substitution of redundant rows or columns.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate an embodiment of theinvention and, together with the description, serve to explain theadvantages and principles of the invention. In the drawings,

[0011]FIG. 1 is a block diagram of the system for testing memory chip;

[0012]FIG. 2a shows a flow chart of the steps for performing an exampletest selection according to one implementation of the present invention;

[0013]FIG. 2b shows a flow chart of the steps for performing an exampletest selection according to another implementation of the presentinvention; and

[0014]FIG. 3 shows an example PRAM test flow according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Reference will now be made in detail to the construction andoperation of preferred implementations of the present invention whichare illustrated in the accompanying drawings.

[0016]FIG. 1 shows a block diagram of the memory chip or integratedcircuit testing system in accordance with the present invention. Testingdevice 100 performs tests on a group of semiconductor memory chips 140,simultaneously. Preferably, 64 chips are tested at a time. Each memorychip has a unique identifier, preferably a fuse identifier having aseries of selectively blown fuses corresponding to a unique binarynumber, located on the memory chip. Processor 110 oversees the testingperformed by the testing device 100 and communicates with memory 120that stores procedures for performing a variety of functions such asthose outlined in the flow charts shown in FIGS. 2-4. In performingthese procedures, the processor 110 accesses a database 130 that storesfuse identifiers in conjunction with test identifiers that identifytests that a specific memory chip failed.

[0017] In a preferred embodiment the database includes data in a formatas shown below in Table 1. The first field indicates the number of teststhat a memory chip failed, a plurality of fields list test numbersdesignating specific tests which the chip failed and the final fieldindicates the unique fuse identifier. TABLE 1 Tests Failed FuseIdentifier Memory Chip 1 3 22 34 79 12345:12:1 Memory Chip 2 1 8812345:12:2 Memory Chip 3 4 22 33 34 79 12345:12:3 Memory Chip 4 3 22 3480 12345:12:4

[0018] Using the example shown in Table 1 the benefits of the presentinvention will be further described. Using the system described in theBackground of the Invention, after faulty memory chips have been setaside for repair, frequently failed tests, not necessarily actuallyfailed tests, are rerun on the memory chips in order to determine thespecific bits that may be faulty. If tests 22, 34, 35, 79, and 80 areconsidered the most commonly failed tests then memory chip 2 will not berepaired because it does not include any bits that will fail the listedtests.

[0019] In the repair step in accordance with the present invention, abetter set of tests will be selected that only includes tests actuallyfailed. This set of tests saves time because fewer tests need to be runand it allows for a more accurate repair. A detailed description of thetesting and repair of semiconductor chips in accordance with the presentinvention will be set forth below.

[0020] First, preferably a group of 64 memory chips is tested beginningwith a first test (step 200). If any one of these memory chips failsthis test (step 205), a test identifier that identifies the failed testis stored in the database in the Tests Failed Field in conjunction withthe fuse identifiers listed in the Fuse Identifier field for thecorresponding failed memory chip(s) (step 210). Next, if none of thememory chips failed or after storing the failed test identifiers, thesystem determines whether another test needs to be performed (step 215).If so, the group of memory chips are passed through steps 200-215 untilno tests remain. The defective chips are then set aside (step 217).Another group of 64 chips is then tested and passed through steps200-215. Defective chips are set aside, and the testing of successivegroups of chips continues until all chips have been tested and alldefective chips have been set aside and identified. The process thencontinues with step 220.

[0021] In one implementation of the present invention, tests that werefailed by a group of the defective memory chips, are ranked beginningwith the most failed test (step 220). The highest ranked test in thegroup is selected to be placed in a set of tests to be repeated on thememory chips (step 225). Tests failed by chips in the group that did notfail the highest ranked test, are then ranked again (step 230). Thehighest ranked test among these remaining tests is also selected andinserted in the set of tests to be repeated (step 235). If any of thedefective memory chips in the group did not fail one of the tests in theset of tests to be repeated (step 240), then steps 230-235 are repeateduntil the set of tests includes at least one test failed by eachdefective memory chip. The final set of tests are then repeated on thedefective memory chips of the group (step 245). Preferably, 32 defectivememory chips are included in each group.

[0022] In another implementation, shown in FIG. 2b, re-testing time isminimized. After each of the memory chips have been tested (step 215),the database includes a plurality of sets of failed tests for eachfailed chip of a group to be repaired such as those shown in Table 1. Aplurality of combinations of tests are generated, wherein eachcombination incudes at least one of the tests in each set of failedtests (step 255). For example, a few combinations of tests to begenerated from Table 1 include, for example (3, 1, 4, and 80); (3, 88,4, and 80); (3, 1, and 22); (22 and 88); and (34 and 88). An amount oftime required to perform each test is known. Therefore, the timerequired to perform each combination of tests may be calculated bysumming the time required for the individual tests (step 260). Thecombination of tests that requires the least amount of time is thenselected (step 265). For instance, the set of tests 22 and 88 will berun instead of tests 34 and 88 when the time required to perform test 22is less than the time required to perform test 34. The selectedcombination of tests are performed on each of the defective memory chipsin the group (step 270).

[0023] The above-described selection of tests is repeated for successivegroups until all defective chips have been repaired.

[0024] As discussed below, a set of tests is repeated on the memory chipin order to determine the location of defective bits or memory cells onthe memory chips. Time will be saved because tests that were not failedby any of the memory chips will not be repeated. Nor will overlappingtests be run, such as when a plurality of memory chips all fail a commontest, only that common test need be repeated.

[0025]FIG. 3 shows an example DRAM test flow according to the presentinvention that begins by testing a memory chip using a hot pregrade step(step 300). The hot pregrade step involves performing tests such asspeed grading, complex margin testing, and parametric testing all ofwhich are performed at a temperature around 85° C. on a testingapparatus such as a circuit tester manufactured by Teradyne, Inc. Asnoted above, preferably, a group of 64 memory chips are tested at atime.

[0026] Margin testing is performed to determine the functionality of amemory chip and to determine what effect voltage has on the write andread functions of the memory chip. This test involves writing to amemory cell in a memory chip and reading from that same cell at avariety of very low and high voltages.

[0027] If it is determined that the memory chip failed any one of thesetests (step 305), then the failed test numbers are stored in database130 (step 210), and the memory chip is placed in a repair bin (step345). If there are any other chips to be tested (step 215) then the nexttest is performed (step 217) and processing continues with step 300.Otherwise, tests are selected, using criteria such as that discussedabove, and repeated (step 350). Any detected failed bits or memory cellsare identified and hot repaired (step 355).

[0028] A memory chip that successfully passed the hot pregrade tests(step 300) is then further tested using burn-in tests (step 310) such asfunctional testing, and “infant mortality” stress which is preferablycarried out for about 80 hours at a temperature of about 127° C. Infantmortalities are chip failures that occur under voltage or temperaturestress. Memory chips include a polysilicon layer that may break off andcross conductive portions on the chip. An oxide layer can form betweenthe broken off piece of the polysilicon layer and the conductiveportions such that the conductive portions remain isolated. However,under voltage or temperature stress the oxide layer breaks down causingthe polysilicon layer to short the conductive portions together.Therefore, by applying voltage or temperature stress to the chip, thesefailures are detected. Cold-burn testing may also be carried out withmargin testing and functional testing at −10° C. to 85° C.

[0029] During the burn-in step (step 310), functional testing isperformed by promoting failure using voltage and temperature stress.When it is determined that the memory chip fails any of the burn-intests (step 315), then processing continues with step 210 as discussedabove. Otherwise, the hot final tests are performed (step 320) for speedverification. These tests include complex margin testing, parametrictesting, and are all preferably performed at 85° C. on a testingapparatus such as one circuit tester manufactured by Teradyne, Inc. Whena memory chip fails any of the hot final tests (step 320), thenprocessing continues with step 210 as discussed above.

[0030] Otherwise, testing continues with the cold final tests (step 330)that are also for speed verification and include complex margin testing,parametric testing, all performed preferably at −5° C. on theabove-described Teradyne circuit tester.

[0031] Hot final and cold final testing are similar speed tests used todetermine whether a memory chip has acceptable access times for thebits, the only difference being the temperature at which these tests arecarried out. In order to determine how fast a chip is, the testingincludes writing to a bit address and a set period of time later,attempting to read that address to determine whether the data is there.If the data is not there, then the memory chip fails this test.

[0032] When a memory chip fails one of the cold final tests (step 330),the failed test numbers are stored in database 130 (step 210), and thememory chip is set aside for repair (step 345). If there are any otherchips to be tested (step 215) then testing of these chips continues withstep 300. Otherwise, tests are selected, using criteria such as thatdiscussed above, and repeated (step 350). Any detected failed bits ormemory cells are identified and cold repaired (step 355). As notedabove, preferably 32 chips are repaired at a time.

[0033] During the repair step identified failed bits or memory cells arerepaired by replacing them with redundant bits or memory cells. Therepaired chip is then preferably re-tested.

[0034] The memory chip is determined to be a good product when thememory chip passes all of the tests (step 340).

[0035] In an alternative embodiment all tests are performed before afailed memory chip is set aside so that the list of failed tests in thedatabase is complete.

[0036] The present invention thus optimizes the testing and repairprocess for semiconductor memory chips. The invention accomplishes thisby only performing redundancy analysis using a group of tests that aspecific memory chip or group of memory chips has failed.

[0037] The foregoing description of a preferred embodiment of theinvention has been presented for purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise form disclosed, and modifications andvariations are possible in light of the above teachings or may beacquired from practice of the invention. For example, the presentinvention is not limited to testing and repair of memory chips, but anyintegrated circuit requiring testing and repair. The embodiment waschosen and described in order to explain the principles of the inventionand its practical application to enable one skilled in the art toutilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated. It isintended that the scope of the invention be defined by the claimsappended hereto, and their equivalents.

We claim:
 1. A method for testing a plurality of integrated circuits,including the steps of: performing a plurality of tests on the pluralityof integrated circuits; identifying integrated circuits that failed atleast one of the plurality of tests and identifying tests failed by theintegrated circuits; and repeating at least one identified failed teston the identified integrated circuits.
 2. A method for testing accordingto claim 1, wherein each of the plurality of integrated circuits has acorresponding unique integrated circuit identifier stored in a memoryand each of the plurality of tests has an associated test identifier,and wherein the step of identifying further includes the step of:storing failed test identifiers in the memory in association with thefailed integrated circuit identifiers.
 3. A method for testing accordingto claim 2, wherein the step of repeating includes selecting tests to berepeated by retrieving at least one of the stored failed testidentifiers.
 4. A method for testing according to claim 3, wherein eachfailed integrated circuit has a set of associated failed testidentifiers stored in the memory, and wherein the step of selectingincludes: comparing sets of failed test identifiers for each of thefailed integrated circuits; selecting a subset of tests that includes atleast one test from each set of failed test identifiers; and repeatingthe subset of tests on the failed integrated circuits.
 5. A method fortesting according to claim 4, wherein the step of selecting a subset oftests includes the steps of: determining an amount of time each testrequires; summing the determined amounts of time for a plurality ofcombinations of tests; and selecting the combination of tests thatrequires a minimal amount of time.
 6. A method for testing according toclaim 4, wherein the step of selecting a subset of tests includes thesteps of ranking the identified failed tests in order of the highestnumber of integrated circuits failing each test; and selecting thehighest ranked test to be in the subset of tests.
 7. A method fortesting according to claim 6, further including the steps of: rankingthe identified failed tests for each of the remaining failed integratedcircuits that did not fail the first of said ranked tests in order ofthe highest number of integrated circuits failing each of said remainingfailed tests; selecting the highest ranked test, of said identifiedfailed tests for each of the remaining integrated circuits, to be in thesubset of tests; and repeating the steps of ranking and selecting untilthere are no identified circuits that did not fail at least one of thetests in the subset of tests.
 8. A method for testing according to claim1 wherein the integrated circuits each include an array of memory cellsand wherein the step of repeating includes the substep of identifying atleast one failed memory cell in the array of memory cells for eachidentified integrated circuit.
 9. A method for testing as recited inclaim 8, further including the step of repairing the identified at leastone failed memory cell in each identified integrated circuit.
 10. Amethod for testing an integrated circuit having an array of memory cellsand an associated integrated circuit identifier stored in a memory, themethod including the steps of: performing a first test on the integratedcircuit, the first test having an associated first test identifier;determining whether the integrated circuit passed the first test;storing a first test identifier in the memory in association with theintegrated circuit identifier when the integrated circuit did not passthe first test; reading test identifiers stored in the memory that areassociated with the integrated circuit identifier; and repeating atleast one test associated with the read test identifiers for the firstmemory chip.
 11. The method for testing according to claim 10, furtherincluding the steps of: performing a second test on the integratedcircuit when the integrated circuit passes the first test; determiningwhether the integrated circuit passed the second test; and storing asecond test identifier in the memory in association with the integratedcircuit identifier when the integrated circuit did not pass the secondtest.
 12. The method for testing according to claim 10, wherein the stepof performing a first test includes performing a plurality of tests eachhaving an associated test identifier and wherein the step of determiningincludes determining whether the integrated circuit failed any one ofthe plurality of tests, wherein the step of storing includes storing acorresponding test identifier in association with an integrated circuitidentifier for each failed test, and wherein the test of repeatingincludes repeating at least one of the tests failed by each failedintegrated circuit.
 13. The method for testing according to claim 12,wherein each failed integrated circuit has a set of associated failedtest identifiers stored in the memory, and wherein the step of selectingincludes: comparing sets of failed test identifiers for each of thefailed integrated circuits; selecting a subset of tests that includes atleast one test from each set of failed test identifiers; and repeatingthe subset of tests on the failed integrated circuits.
 14. A method fortesting according to claim 13, wherein the step of selecting a subset oftests includes the steps of: determining an amount of time each testrequires; summing the determined amounts of time for a plurality ofcombinations of tests; and selecting the combination of tests thatrequires a minimal amount of time.
 15. A method for testing according toclaim 13, wherein the step of selecting a subset of tests includes thesteps of ranking the identified failed tests in order of the highestnumber of integrated circuits failing each test; and selecting thehighest ranked test of said identified failed tests for each of theremaining integrated circuits to be in the subset of tests.
 16. A methodfor testing according to claim 15, further including the steps of:ranking the identified failed tests for each of the remaining failedintegrated circuits that did not fail the first of said ranked tests inorder of the highest number of integrated circuits failing each of saidremaining failed tests; selecting the highest ranked test, of saididentified failed tests for each of the remaining integrated circuits,to be in the subset of tests; and repeating the steps of ranking andselecting until there are no identified circuits that did not fail atleast one of the tests in the subset of tests.
 17. An apparatus fortesting a plurality of integrated circuits, including: means forperforming a plurality of tests on the plurality of integrated circuits;means for identifying integrated circuits that failed at least one ofthe plurality of tests and identifying tests failed by the integratedcircuits; and means for repeating at least one identified failed test onthe identified integrated circuits.
 18. An apparatus for testingaccording to claim 17, wherein each of the plurality of integratedcircuits has a corresponding unique integrated circuit identifier storedin a memory and each of the plurality of tests has an associated testidentifier, and wherein the means for identifying further includes:means for storing failed test identifiers in the memory in associationwith the failed integrated circuit identifiers.
 19. An apparatus fortesting according to claim 18, wherein the means for repeating includesmeans for selecting tests to be repeated by retrieving at least one ofthe stored failed test identifiers.
 20. An apparatus for testingaccording to claim 19, wherein each failed integrated circuit has a setof associated failed test identifiers stored in the memory, and whereinthe means for selecting includes: means for comparing sets of failedtest identifiers for each of the failed integrated circuits; means forselecting a subset of tests that includes at least one test from eachset of failed test identifiers; and means for repeating the subset oftests on the failed integrated circuits.
 21. An apparatus for testingaccording to claim 20, wherein the means for selecting a subset of testsincludes: means for determining an amount of time each test requires;means for summing the determined amounts of time for a plurality ofcombinations of tests; and means for selecting the combination of teststhat requires a minimal amount of time.
 22. An apparatus for testingaccording to claim 20, wherein the means for selecting a subset of testsincludes: means for ranking the identified failed tests in order of thehighest number of integrated circuits failing each test; and means forselecting the highest ranked test to be in the subset of tests.
 23. Anapparatus for testing according to claim 22, further including: meansfor ranking the identified failed tests for each of the remaining failedintegrated circuits that did not fail the first of said ranked tests inorder of the highest number of integrated circuits failing each of saidremaining failed tests; means for selecting the highest ranked test, ofsaid identified failed tests for each of the remaining integratedcircuits, to be in the subset of tests; and means for repeatedlyactivating the means for ranking and selecting until there are noidentified circuits that did not fail at least one of the tests in thesubset of tests.
 24. An apparatus for testing according to claim 17wherein the integrated circuits each include an array of memory cellsand wherein the means for repeating includes a means for identifying atleast one failed memory cell in the array of memory cells for eachidentified integrated circuit.
 25. An apparatus for testing as recitedin claim 24, further including a means for repairing the identified atleast one failed memory cell in each identified integrated circuit. 26.An apparatus for testing an integrated circuit having an array of memorycells and an associated integrated circuit identifier stored in amemory, including: means for performing a first test on the integratedcircuit, the first test having an associated first test identifier;means for determining whether the integrated circuit passed the firsttest; means for storing a first test identifier in the memory inassociation with the integrated circuit identifier when the integratedcircuit did not pass the first test; means for reading test identifiersstored in the memory that are associated with the integrated circuitidentifier; and means for repeating at least one test associated withthe read test identifiers for the first memory chip.
 27. An apparatusfor testing according to claim 26, further including: means forperforming a second test on the integrated circuit when the integratedcircuit passes the first test; means for determining whether theintegrated circuit passed the second test; and means for storing asecond test identifier in the memory in association with the integratedcircuit identifier when the integrated circuit did not pass the secondtest.
 28. An apparatus for testing according to claim 26, wherein themeans for performing a first test includes means for performing aplurality of tests each having an associated test identifier and whereinthe means for determining includes means for determining whether theintegrated circuit failed any one of the plurality of tests, wherein themeans for storing includes means for storing a corresponding testidentifier in association with an integrated circuit identifier for eachfailed test, and wherein the test of repeating includes means forrepeating at least one of the tests failed by each failed integratedcircuit.
 29. An apparatus for testing according to claim 18, whereineach failed integrated circuit has a set of associated failed testidentifiers stored in the memory, and wherein the means for selectingincludes: means for comparing sets of failed test identifiers for eachof the failed integrated circuits; means for selecting a subset of teststhat includes at least one test from each set of failed testidentifiers; and means for repeating the subset of tests on the failedintegrated circuits.
 30. An apparatus for testing according to claim 29,wherein the means for selecting a subset of tests includes: means fordetermining an amount of time each test requires; means for summing thedetermined amounts of time for a plurality of combinations of tests; andmeans for selecting the combination of tests that requires a minimalamount of time.
 31. An apparatus for testing according to claim 29,wherein the means for selecting a subset of tests includes: means forranking the identified failed tests in order of the highest number ofintegrated circuits failing each test; and means for selecting thehighest ranked test to be in the subset of tests.
 32. An apparatus fortesting according to claim 31, further including: means for ranking theidentified failed tests for each of the remaining failed integratedcircuits that did not fail the first of said ranked tests in order ofthe highest number of integrated circuits failing each of said remainingfailed tests; means for selecting the highest ranked test, of saididentified failed tests for each of the remaining integrated circuits,to be in the subset of tests; and means for repeatedly activating themeans for ranking and selecting until there are no identified circuitsthat did not fail at least one of the tests in the subset of tests.